Dynamic Random Access Memory (DRAM) serves as a core memory component widely deployed in cloud servers, personal computers, smartphones and various electronic devices. Renowned for low latency, high bandwidth, fast computing speed, high integration density and mature manufacturing processes, DRAM has become a foundational solution for in-memory computing systems.
Structurally, a complete DRAM device consists of peripheral logic circuits and storage matrix arrays, featuring inherent volatility and mandatory refresh operations. In terms of performance trade-offs, DRAM delivers faster read and write speeds than NAND flash memory yet with smaller storage capacity; compared with SRAM, it runs slightly slower but supports far larger capacity. Balancing access speed and storage volume, DRAM acts as a critical cache medium bridging high-speed core processors and low-speed external storage.
The global DRAM market features a highly concentrated competitive landscape, long dominated by three leading manufacturers: Samsung Electronics, SK Hynix and Micron. According to data from market research firm Omdia, Samsung Electronics holds a 42.8% share of the global DRAM market, with SK Hynix and Micron occupying substantial market positions collectively. The three giants accounted for over 90% of the global DRAM market share in 2022. Meanwhile, domestic semiconductor enterprises such as GigaDevice are steadily expanding their market influence and breaking the long-term monopoly pattern.
Basic Structure and Working Principle of DRAM
The standard DRAM storage cell adopts a classic 1T-1C structure, composed of one field-effect transistor and one storage capacitor. The gate of the transistor is connected to the word line, its drain terminal links to the bit line through contact points, and the source terminal connects to the capacitor via storage nodes. Serving as a controllable switch, the transistor controls the capacitor to store positive or negative charges, realizing the storage of binary data bits.
When the transistor is turned off, a stable operating bias voltage is applied to the capacitor to retain stored charges. When activated, the transistor conducts electricity, allowing the capacitor’s internal charges to flow into the bit line and generate potential changes. Connected sensing amplifiers capture, amplify and detect these subtle potential variations, enabling accurate data reading.
Based on capacitor fabrication methods, mainstream DRAM is categorized into stacked-capacitor and deep-trench-capacitor types. Stacked DRAM arranges capacitors above transistor gates, while trench DRAM embeds capacitors below the gate structure. As semiconductor process nodes continue to shrink, deep trench etching and thin-film deposition have become increasingly technically challenging, leading to the gradual phasing out of trench DRAM in industrial production.
To adapt to shrinking capacitor dimensions, suppress leakage current and boost capacitance performance, DRAM capacitor stacking structures have evolved from the traditional Silicon-Insulator-Silicon (SIS) architecture to the advanced Metal-Insulator-Metal (MIM) structure. MIM capacitors adopt high-dielectric-constant materials including ZrO₂, HfO₂, Al₂O₃ and Ta₂O₅ as dielectrics, paired with metal electrodes such as TiN, WN, W and Ru, effectively optimizing overall capacitive performance and stability.
DRAM Technology Evolution and Process Node Iteration
The origin of DRAM technology dates back to the 1960s, when metal-oxide-semiconductor (MOS) technology was first applied to memory chips with initial storage capacity at the kilobit level. A landmark upgrade came in 1996 with the introduction of Double Data Rate (DDR) technology, which enables data transmission at both the rising and falling edges of each clock cycle, greatly improving memory operating speed. Continuous iterations of DDR technology have driven memory capacity from KB and GB levels to today’s high-capacity single-stick configurations. The final specification of DDR5 SDRAM released by the Solid State Technology Association has become a milestone in the development of modern computer memory.
Over the past few decades, continuous process scaling and improved integration density have fueled exponential growth in the number of storage units on DRAM chips. The 20nm process stands as a mature mass-production node in the industry, with 1X (16–19nm) and 1Y (14–16nm) DRAM products widely commercialized by major manufacturers. Samsung, Micron and SK Hynix have successively launched advanced D1z (13–15nm) and D1a (11–13nm) processes, which have been applied to mass production of DDR4, DDR5 and LPDDR5 products. Current mainstream DRAM chips belong to the 10-nanometer process generation, with the half-pitch of active regions in storage arrays scaling down from 19nm to 10nm.
DRAM process nodes have kept shrinking from 1X (16–19nm) in 2016, 1Y (14–16nm) in 2018 to 1Z (12–14nm) in 2020, bringing significant improvements in chip performance and energy efficiency. SK Hynix’s self-developed HBM2E technology has achieved a substantial leap in data processing speed. The fifth-generation 10nm-class advanced DRAM processes have been widely adopted, named 1β DRAM by Micron and 1b DRAM by Samsung. Samsung has also unveiled its next-generation 1b DRAM roadmap and plans to launch innovative 4F Square DRAM technology in 2025.
DDR5 delivers comprehensive upgrades compared with DDR4. Its initial operating frequency starts at 4800MHz, with mainstream products reaching approximately 7600MHz. It supports higher single-die density up to 16GB and enables single memory module capacity of 128GB or 256GB, while achieving lower power consumption. The optimized dual-channel architecture further enhances bandwidth and reduces latency. Thanks to these advantages, DDR5 exhibits outstanding performance in high-performance computing, large-scale cloud data centers, graphic rendering, film production and high-frequency financial trading. In actual gaming tests, DDR5 platforms deliver higher average and minimum frame rates, with 6% lower CPU usage and 4% higher GPU utilization than traditional DDR4 platforms.
3D DRAM and Peripheral Circuit Innovation
3D DRAM technology has become a key direction for breaking traditional planar process limitations. SK Hynix adopts Indium-Gallium-Zinc Oxide (IGZO) as a new channel material for 3D DRAM R&D, effectively addressing bandwidth and latency bottlenecks. Samsung is developing vertical channel transistor architecture, namely 4F Square technology, which stacks transistors vertically to drastically boost storage density and overall performance. The company has successfully realized 16-layer stacking for next-generation 3D DRAM products and plans to scale down key dimensions to 8–9nm by 2027–2028.
These technological breakthroughs greatly expand storage capacity, while vertical channel transistors and high-bandwidth memory solutions deliver higher data transmission bandwidth and faster processing speed, effectively alleviating bandwidth pressure in data-intensive scenarios such as artificial intelligence and big data analysis.
In addition to core storage arrays, complete DRAM functionality relies on auxiliary peripheral circuits, including address decoders, sensing amplifiers and output buffers. Peripheral transistors are divided into three categories with distinct performance requirements: general logic transistors require excellent short-channel control, high on-current and low off-current; analog sensing amplifiers demand low threshold voltage and minimal mismatch; row decoders adopt thick gate oxide layers to withstand high bias voltages.
All peripheral transistors face strict thermal stability challenges. They must endure multiple high-temperature heat treatments during the fabrication of storage capacitors and access transistors, requiring stable performance under 550–600°C annealing temperatures for several consecutive hours. To control manufacturing costs, the memory industry universally adopts a unified process platform for all types of peripheral transistors.